The fabrication of deep trenches in semiconductor dielectrics is one method of making metallic wires, referred to as interconnects. A deep trench of somewhat trapezoidal shape is etched out of a dielectric layer by a commonly used dry etch method known as reactive ion etching (RIE). There is today an ever increasing need to make the deep trenches more narrow to conserve space on the substrate and, hence, to increase productivity. This reduction process is commonly referred to as scaling. The direct result of scaling is that the width of the deep trench ends up substantially reduced. In order to maximize the cross-sectional area of the interconnect, and thus reduce its wire resistance, its depth must be maintained or increased. Such a situation leads to a high aspect ratio, which is the ratio of the depth of the etched structure relative to its width.
With the requirement of scaling, the control of deep trench side wall passivation has become a fundamental issue and an impediment in achieving deeper trenches. During deep trench etching, the etching process may include simultaneous etching and deposition of a sidewall passivation film. The conventional RIE process is designed in such a manner that the controlled growth of the passivation film prevents isotropic etching to help control the deep trench profile. However, the presence of a thick passivation film on the entire inner surface of the deep trench during the etch process leads to a significantly slower etch rate. The slower etch rate is also due to a high aspect ratio of the deep trenches as noted above. This aspect ratio dependent slowdown of the etch rate is called RIE lag. A result of RIE lag is that smaller width trenches etch less deep than wider width trenches during a given etching timeframe. Thus, when the trenches are filled with metal to form an interconnect, metal with smaller widths are shallower and metal with larger widths are deeper.
Due to misprocessing, poor process setup, etc., RIE lag can cause wide width metal to short to underlying metal even though smaller width metal have depths that are on target and are not shorted. Expensive analysis techniques, such as scanning transmission electron microscopy (STEM), transmission electron microscopy (TEM) and/or scanning electron microscopy (SEM), are typically required to determine the amount of RIE lag and potentially the cause of a failure (e.g., short).